1. Field of the Invention
The field of the invention pertains to random access computer memories RAM of the magnetic or MOS type and more particularly to an apparatus and method for latching the output of a RAM substantially instantaneously with the appearance of data at the output of the RAM.
2. Description of the Prior Art
Random access memories either of the magnetic core type or of the MOS type generally require additional operations to be performed on the memory after read-out or write. For example, in the magnetic core memory read-out is effected by destroying the data content of the memory. To preserve the data content of the memory, a further write operation is required after read-out. However, it is not desirable or efficient to add the time required for read-writing information back into the memory to the total access time of the memory. Accordingly, the read-out data is preserved in some form of latch which may typically be a flip-flop. However, flip-flops add to total access time to store and retain the output information. Accordingly, the total access time of a memory requiring this type of latch is increased by its use. Similarly MOS memories require periodic refreshing and it is not desirable or efficient to refresh such memories during the time that information is being accessed from the memory. Accordingly, any type of latch which tends to increase the access time steals time from other operations such as refreshing, which could be performed at a time other than during access time.
What is needed therefore is a latching circuit or circuits in combination with the RAM wherein the data output does not have to pass through the latching circuit itself, but is latched substantially instantaneously to its one or zero state as soon as it appears on the output of the RAM.
In the above subject Intel reference incorporated herein by reference, there is described an MOS memory chip with a tri state enable of the type utilized in the invention. This enable permits the output to appear substantially instantaneously to the input of the MOS memory. However, since the output follows the input, when the input enable signal is removed, so is the output. What is further needed is that this output remain latched to its input state even though the input enable signal is removed. To fully appreciate the problem, a brief description of this prior art latch will first be given utilizing FIGS. 1-3.
Referring to FIG. 1 there is shown a block diagram of a typical prior art MOS memory chip having a storage capacity for 4,096 bits; also shown as part of the semiconductor memory chip is the appurtenant circuit utilized for addressing, reading and writing into the semiconductor memory. The memory array 102 has 4,096 1 bit positions arranged in an array of 64 columns and 64 rows. Each storage cell in the memory array is implemented with a single transistor and a storage capacitor and are called single transistor cells. Any memory cell may be accessed by the coincidence of addresses A.sub.0 -A.sub.5 defined by row decode in buffer register 101 and column select addresses A.sub.6 -A.sub.11 defined by column decode and buffer register 106. The timing control generator 103 provides the internal timing signals for decoding, read/write strobing, data gating and output gating. The timing circuits are activated by the positive-going edge of a chip enable signal CE. The leading edge of the chip enable CE signal also latches address buffer registers 101 and 106. Since the addresses are latched shortly after chip enable goes high, the address may be changed long before the memory cycle is completed thus shortening the set up for the next cycle. With the address thus properly selected, the chip select CS signal controls the data I/O gating circuits 105 internal to the entire semiconductor chip of FIG. 1. When the chip select signal CS is high, the output data buffer in the I/O unit 105 is in a high impedance state and the data in buffer in the I/O unit 105 is electrically isolated from the data-in input pin D.sub.in. Since the chip select signal CS controls the internal data buffers and not the timing generators or address buffers, refreshing of the chip may be done with the chip select signal CS high by initiating a read/refresh or write cycle. The write enable signal WE permits the data-in in the data-in buffer (not shown) to be written in the memory cell selected by the coincidence of addresses A.sub.0 -A.sub.5 and A.sub.6 -A.sub.11.
Three power supplies are required relative to ground for the chip of FIG. 1. V.sub.DD supplies +12 volts to chip enable signal CE. V.sub.BB is a minus volt power supply and V.sub.CC is +5 volts.
FIG. 2 shows the detailed circuitry for the implementation of a single storage cell implemented with a single transistor 201 and a storage capacitor C.sub.STG 202. A charge on storage capacitor 202 is gated to the bit sense line 203 by the MOS transistor 204 connected to the column sense line 205. (Note that for a given column select, 64 storage devices are gated to the respective 64 bit sense lines).
To illustrate the operation of the circuit, first consider a read operation wherein the storage capacitor C.sub.STG 202 is discharged and node 1 is at ground. With the bit sense lines 203 precharged to V' by transistor 201 and allowing time for the stabilization of the address decoders, the selected column select line is caused to go high, causing transistor 204 to turn on, thus electrically connecting the storage capacitor C.sub.STG 202 to the bit sense line. At this time, the charge on capacitor 206 which is proportional to the precharge voltage V' is redistributed between capacitor 206 and capacitor 202. However, since the charge in capacitor 206 is much larger than the charge on capacitor 202 the voltage on the bit sense line will be very small. The sense amplifier 207 is such that it detects very small changes in bit sense line voltage and latches in a state near V.sub.SS (ground) of V.sub.DD (plus 12 volts), depending on the state of the storage cell. Note that during this read operation of the storage cell 202, the original data (i.e. charge) on the storage cell is destroyed. Data is rewritten back into the storage capacitor 202 by the sense amplifier 207 after it has latched in the proper state. For example, if the storage capacitor 202 was initially charged to approximately 10 volts, the sense amplifier 207 will latch the bit sense line to approximately 10 volts and, since the column select line 205 is high, the original data is automatically rewritten into storage capacitor 202.
FIG. 3 is a plot of the voltage on the bit sense line and shows the 3 states in which the memory may latch -- i.e. the logic 0 state, the logic 1 state and the neuter or "I don't care" state.
A complete description of the details of the above prior art circuit is described in the above referenced Intel reference. Also the chip itself is commercially available from the Intel Corporation and is identified as the Intel Memory 2107B. Note that only one tri state circuit is provided for each memory cell. Additionally, prior art RAM's of the magnetic core type are well known, see U.S. Pat. No. 3,181,131 issued Apr. 27, 1965 and incorporated herein by reference.